Colloquium: Hussam Amrouch
Wednesday, February 12
3:30 p.m.
Avery 115
Reception held immediately following colloquium at 4:30 p.m.
“Challenges and Opportunities in Computing with NCFET: A Journey from Device Physics to MultiCore Processors”
Abstract: The inability of transistors to switch faster than 60mV/decade is one of the fundamental limits in physics for technology scaling, which had prevented the continuation of Dennard’s scaling more than a decade ago. As a result, on-chip power densities continuously increases with every new generation leading to excessive temperatures that seriously degrade the reliability of chips. In addition, technology scaling is reaching limits in which displacing few atoms within transistors, due to aging phenomena such Bias Temperature Instability (BTI) and Hot-Carrier Injection (HCI), provokes uncertainty that may cause catastrophic errors during operation. Due to the inevitable need to include wider and wider timing guardbands towards sustaining reliability for the entire projected lifetime, the customary trend in which performance is gained with technology scaling becomes very difficult.
Negative-Capacitance Field-Effect Transistor (NCFET) is emerging as a promising new technology with various advantages as well as new challenges compared to conventional CMOS technology. NCFET technology can operate at lower voltage while they may still provide the same level of performance. While the exact trade-offs are still to be explored, it is obvious that lower power designs are possible. However, employing NCFET technology will have significant effect on circuits, architecture and system level management techniques. For example, as opposed to conventional CMOS technology, the power consumption: particularly the leakage current may have an inverse tendency as a function of the supply voltage. That means that conventional power management techniques for multi-core will not work any longer since they would lead to sub-optimal results depending on system-level workload properties. These are some examples of the implications at the architectural and system level that will be discussed during this talk after a short general introduction to the NCFET technology.
Short Bio: Dr. Hussam Amrouch is a Research Group
Leader at the Chair for Embedded Systems (CES),
Karlsruhe Institute of Technology (KIT), Germany, where he
is leading of the Dependable Hardware research group. He
received his Ph.D. degree from KIT in 2015 with the highest
distinction. His main research interests are design for
reliability from physics to systems in advanced and
emerging technologies. He published so far more than 70
publications in multidisciplinary research fields starting from
semiconductor physics to the circuit level all the way up to
the system level. He holds 7 HiPEAC paper awards and he
has three best paper nominations at DAC’16, DAC’17 and DATE’17 for his work on reliability. He currently serves as Associate Editor at Integration, the VLSI Journal.